System-level analysis of soft error rates and mitigation trade-off explorations
conference paper
This paper presents a novel system-level analysis of soft error rates (SER) based on the Transaction Level Model (TLM) of a targeted System-On-a-Chip (SoC). This analysis runs 1000x faster than the conventional SoC analysis using a gate-level model. Moreover, it allows accurate prediction in the early design phase of a SoC, when only limited application details are available. Preliminary validation results from accelerated SER tests on the physical system have shown that the analysis can predict the SER with a reasonable accuracy (within 5x of the results from tests on physical systems). This system-level analysis is particularly suitable to handle the black-box models for industrial semiconductor IP libraries. Based on this system-level analysis, we also propose a SE mitigation solution using selective protection of SRAM of a SoC. This solution provides a series of trade-offs between the system dependability and cost (in terms of silicon area).
Topics
Accurate predictionBlack-box modelEarly design phaseIP libraryPhysical systemsReasonable accuracySelective protectionSilicon areaSoft error rateSystem dependabilitySystem-level analysisSystem-on-a-chipTransaction-level modelValidation resultsApplication specific integrated circuitsMicroprocessor chipsProgrammable logic controllers
TNO Identifier
954156
ISSN
15417026
ISBN
9781424454310
Publisher
IEEE
Article nr.
5488685
Source title
Proceedings IEEE International Reliability Physics Symposium, IRPS 2010, 2 May 2010 through 6 May 2010
Pages
1014-1018
Files
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