Influence of gate patterning on line edge roughness

article



Leunissen, L.H.A.

Jonckheere, R.

Ronse, K.

Derksen, G.B.
The transfer of the line edge roughness (LER) of the resist pattern into the poly-silicon layer was investigated. The resist line patterns were generated with some additional programmed LER. The linewidth decreases approximately 10 nm between the two measurements. The results show that the LER pattern is transferred to large extent into the poly-Si.
Topics









Computer simulationComputer softwareDiffractionElectron beam lithographyEtchingPolysiliconScanning electron microscopyLine edge roughness (LER)Linewidth roughness (LWR)Gates (transistor)
TNO Identifier
237380
Repository link
https://resolver.tno.nl/uuid:789035b2-2632-4a5d-95d9-a6484b9fdc78
ISSN
10711023
Source
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 21(6), pp. 3140-3143.
Pages
3140-3143
Files
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