Impact of etch stop layer on negative bias illumination stress of amorphous Indium Gallium Zinc Oxide transistors
article
In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.
TNO Identifier
868256
ISSN
1930-8876
ISBN
978-1-4799-4376-0
Publisher
IEEE
Source title
2014 44th European Solid State Device Research Conference (ESSDERC)
Pages
302-304
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