1000-Pixels per Inch Transistor Arrays Using Multi-Level Imprint Lithography

article







Dogan, T.

Riet, J. de

Bel, T.

Katsouras, I.

Witczak, L.

Kronemeijer, A.J.

Janssen, R.A.

Gelinck, G.H.
Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7 μm, field-effect mobility of 10 cm2 V−1 s−1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.
Topics


High-resolution thin film transistor arrayAmorphous Indium Gallium Zinc Oxide thin film transistorMulti-level nanoimprint lithography
TNO Identifier
880331
Repository link
https://resolver.tno.nl/uuid:ceb6345d-185d-4c49-a629-9dbe002120dd
ISSN
0741-3106
Source
IEEE Electron device letters, 41(8), pp. 1217-1220.
Publisher
IEEE
Pages
1217-1220
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