Very low temperature epitaxy of Group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

article

















Porret, C.

Hikavyya, A.

Gomez Granados, J.F.

Baudot, S.

Vohra, S.

Kunert, B.

Douhard, B.

Bogdanowicz, J.

Schaekers, M.

Kohen, D.

Margetis, J.

Tolle, J.

Lima, L.P.B.

Sammak, A.

Scappucci, G.

Rosseel, E.

Langer, R.

Loo, R.
As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.
TNO Identifier
875516
Repository link
https://resolver.tno.nl/uuid:eac7f065-dc87-4f8d-8ec7-be246db6e091
Source
ECS Transactions, 86(7), pp. 163-175.
Publisher
The Electrochemical Society
Collation
13
Place of publication
Pennington, NJ, USA
Pages
163-175
Files
To receive the publication files, please send an e-mail request to TNO Repository.