A sparse spin qubit array with integrated control electronics
conference paper
Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.
TNO Identifier
875425
Publisher
IEEE
Source title
2019 IEEE International Electron Devices Meeting (IEDM), San Fransisco, CA, USA, 7-11 December 2019
Collation
4 p.
Files
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