Robust co-synthesis of embedded control systems with occasional deadline misses
conference paper
Feedback control applications are robust to occasional deadline misses. This opens up the possibility of saving scarce (computation and communication) resources on embedded platforms. Stability and performance requirements of a control loop impose restrictions on acceptable patterns of deadline misses (e.g., not too many misses in a row). Such requirements are captured by (m,k)-firmness conditions. That is, at least m control computation jobs must meet deadlines in any k consecutive jobs. (m,k)-firm design requires (i) representation of stability and performance requirements in terms of (m,k)-firm deadlines (ii) controller synthesis taking into account the (m,k)-firmness parameters (iii) schedule analysis to verify guarantees on meeting the firmness conditions. We present a co-synthesis framework for these three design components and illustrate its applicability with examples. © 2018 IEEE.
Topics
TNO Identifier
843771
ISSN
9781538659922
Publisher
Institute of Electrical and Electronics Engineers Inc.
Article nr.
8474138
Source title
24th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2018, 2 July 2018 through 4 July 2018
Editor(s)
Maniatakos M.
Alexandrescu, D.
Gizopoulos, D.
Papavramidou, P.
Alexandrescu, D.
Gizopoulos, D.
Papavramidou, P.
Pages
127-130
Files
To receive the publication files, please send an e-mail request to TNO Repository.