An experimental microarchitecture for a superconducting qantum processor
conference paper
Quantum computers promise to solve certain problems that are intractable for classical computers, such as factoring large numbers and simulating quantum systems. To date, research in quantum computer engineering has focused primarily at opposite ends of the required system stack: devising high-level programming languages and compilers to describe and optimize quantum algorithms, and building reliable low-level quantum hardware. Relatively little attention has been given to using the compiler output to fully control the operations on experimental quantum processors. Bridging this gap, we propose and build a prototype of a flexible control microarchitecture supporting quantum-classical mixed code for a superconducting quantum processor. The microarchitecture is based on three core elements: (i) a codeword-based event control scheme, (ii) queue-based precise event timing control, and (iii) a flexible multilevel instruction decoding mechanism for control. We design a set of quantum microinstructions that allows flexible control of quantum operations with precise timing. We demonstrate the microarchitecture and microinstruction set by performing a standard gate-characterization experiment on a transmon qubit. © 2017 Association for Computing Machinery.
Arm; Cavium; et al.; Intel; Oracle; Qualcomm
Arm; Cavium; et al.; Intel; Oracle; Qualcomm
Topics
Quantum (micro-) architectureQuantum instruction set architecture (QISA)QuMAQuMISSuperconducting quantum processorComputer hardwareComputer programming languagesComputer systems programmingHigh level languagesProgram compilersProgram processorsQuantum computersQuantum opticsQuantum theoryComputer engineeringHigh-level programming languageInstruction set architectureMicro architecturesQuantum operationsQuantum processorsComputer architecture
TNO Identifier
782457
ISSN
10724451
ISBN
9781450349529
Publisher
IEEE Computer Society
Source title
50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017. 14 October 2017 through 18 October 2017
Pages
813-825
Files
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