A new concept for spatially divided Deep Reactive Ion Etching with ALD-based passivation
conference paper
Conventional Deep Reactive Ion Etching (DRIE) is a plasma etch process with alternating half-cycles of 1) Si-etching with SF6 to form gaseous SiFx etch products, and 2) passivation with C4F8 that polymerizes as a protecting fluorocarbon deposit on the sidewalls and bottom of the etched features. In this work we report on a novel alternative and disruptive technology concept of Spatially-divided
Deep Reactive Ion Etching, S-DRIE, where the process is converted from the time-divided into the spatially divided regime. The spatial division can be accomplished by inert gas bearing ‘curtains’ of heights down to ~20 um. These curtains confine the reactive gases to individual (often linear) injection slots constructed in a gas injector head. By horizontally moving the substrate back and forth under the head one can realize the alternate exposures to the overall cycle. A second improvement in the spatially divided approach is the replacement of the CVD-based C4F8 passivation steps by ALD-based oxide (e.g. SiO2) deposition cycles. The method can have industrial
potential in cost-effective creation of advanced 3D interconnects (TSVs), MEMS manufacturing and advanced patterning, e.g., in nanoscale transistor line edge roughness using Atomic Layer Etching.
Deep Reactive Ion Etching, S-DRIE, where the process is converted from the time-divided into the spatially divided regime. The spatial division can be accomplished by inert gas bearing ‘curtains’ of heights down to ~20 um. These curtains confine the reactive gases to individual (often linear) injection slots constructed in a gas injector head. By horizontally moving the substrate back and forth under the head one can realize the alternate exposures to the overall cycle. A second improvement in the spatially divided approach is the replacement of the CVD-based C4F8 passivation steps by ALD-based oxide (e.g. SiO2) deposition cycles. The method can have industrial
potential in cost-effective creation of advanced 3D interconnects (TSVs), MEMS manufacturing and advanced patterning, e.g., in nanoscale transistor line edge roughness using Atomic Layer Etching.
TNO Identifier
466712
Publisher
IOP
Source title
E-MRS 2012 Spring Meeting: Symposium M
Place of publication
Eindhoven
Files
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