A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS
conference paper
Applications like wireless sensor nodes require ultra low-power receivers with power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications [1], [2]. This work describes the implementation of an 8bit asynchronous SAR ADC that achieves a 30fJ/Conversion-step power-efficiency for sampling rates between 10kS/s and 10MS/s. ©2010 IEEE.
Topics
TNO Identifier
461586
ISSN
01936530
ISBN
9781424460342
Article nr.
05433967
Source title
2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, 7 February 2010 through 11 February 2010, San Francisco, CA
Pages
388-389
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