2D and 3D interconnect fabrication by picosecond Laser Induced Forward Transfer
conference paper
Interconnects are an important cost driver in advanced 3D chip packaging. This holds for Through Silicon Vias (TSV) for chip stacking, but also for other integrated Si-technology. Especially in applications with a low number (<100 mm-2) of relatively large (10-2- um diameter), high aspect ratio (1:5-1:20) vertical interconnects (TSV's), conventional wafer level plating processes are slow and become cumbersome with increasing aspect ratio, thus becoming cost ineffective. Hence, industrially feasible alternative deposition processes are of interest for advanced interconnects. LIFT is a maskless direct-write process with industrial potential. It is a single step, dry process under atmospheric (clean room) conditions. It is suitable for different types of interconnect fabrication, without the need for wet chemicals or high temperatures. The paper reports on the investigations towards minimum feature size, morphology and resistivity of 2D and 3D copper structures built using picosecond LIFT. It will be shown that very promising structures could be realized. Possible applications for micro electronics manufacturing are discussed.
Topics
TNO Identifier
445783
ISBN
9780955308291
Source title
11th International Conference of the European Society for Precision Engineering and Nanotechnology, EUSPEN 2011, 23 May 2011 through 26 May 2011
Pages
484-487
Files
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