Novel approaches for low-cost through-silicon vias

Bullema, J.E.; Bressers, P.; Oosterhuis, G.; Mueller, M.; Huis in 't veld, A.J.; Roozeboom, F.

Novel approaches for low-cost through-silicon vias

conference paper

2011

Bullema, J.E.

Bressers, P.

Oosterhuis, G.

Mueller, M.

Huis in 't veld, A.J.

Roozeboom, F.

3D stacking of integrated circuits is an emerging packaging technology to enable a high degree of functional integration and miniaturization. Footprint reduction in 3D stacking can be achieved by use of Through Silicon Vias (TSV). Creation of TSVs with Deep Reactive Ion Etching (DRIE), laser drilling and pulse reverse plating is established technology. Current TSV technologies are considered as high cost processes due to expensive equipment and long processing times. In this paper three novel technological approaches to create TSVs are described that potentially can lead to a creation of low-cost Through Silicon Vias. The technologies in development discussed here, were identified based upon cost of ownership analysis of current TSV creation processes. The paper presents the first results of the different approaches.

Topics

3D stacking Cost of ownership Creation process Deep Reactive Ion Etching Electrochemical machining Laser drilling Laser Induced Forward Transfer Packaging technologies Processing time Pulse reverse plating Through silicon vias

TNO Identifier

445778

Repository link

https://resolver.tno.nl/uuid:5c901154-2e6f-4b64-abc6-6e02ecba76ab

ISBN

9780956808608

Source

18th European Microelectronics and Packaging Conference, EMPC-2011, 12-15 September 2011, Brighton, UK

Article nr.

6142399

Files

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Novel approaches for low-cost through-silicon vias

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