A single Chip Implementation for Fast Convolution of Long Sequences
conference paper
Usually, long convolutions are computed by programmable DSP boards using long FFTs. Typical operational requirements such as minimum power dissipation, minimum volume and high dynamic range/accuracy, make this solution often inefficient and even unacceptable. In this paper we present a single chip floating point solution for large convolution problems. It is based on an algorithm that maps long convolutions on
short FFTs without affecting the optimum complexity O(N log N). The chip contains a highly parallelized short length FFT core enabling us to compute an FFT completely, without external FFT working memory intervention. The FFT core contains a set of fully parallelized radix 2 processing cores based on a hybrid floating point data format. The proposed implementation of the arithmetic blocks is the result of a trade off between maximum accuracy, maximum dynamic range and minimum chip area. The convolution chip will be used in a realtime Synthetic Aperture Radar (SAR) imaging processor developed for on-board aircraft or satellite processing.
short FFTs without affecting the optimum complexity O(N log N). The chip contains a highly parallelized short length FFT core enabling us to compute an FFT completely, without external FFT working memory intervention. The FFT core contains a set of fully parallelized radix 2 processing cores based on a hybrid floating point data format. The proposed implementation of the arithmetic blocks is the result of a trade off between maximum accuracy, maximum dynamic range and minimum chip area. The convolution chip will be used in a realtime Synthetic Aperture Radar (SAR) imaging processor developed for on-board aircraft or satellite processing.
Topics
TNO Identifier
95030
Publisher
STW
Source title
Proceedings of the ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Mierlo, The Netherlands, November 27-28, 1996
Editor(s)
Veen, J.P.
Place of publication
Utrecht
Pages
385-390
Files
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