Searched for: subject%3A%22Wafer%255C%2Blevel%255C%2Bpackaging%22
(1 - 4 of 4)
document
Hoppenbrouwers, M.B. (author), Oosterhuis, G. (author), Knippels, G. (author), Roozeboom, F. (author)
bookPart 2014
document
Taklo, M.M.V. (author), Vard√ły, A.S. (author), de Wolf, I. (author), Simons, V. (author), van de Wiel, H.J. (author), van der Waal, A. (author), Lapadatu, A. (author), Martinsen, S. (author), Wunderle, B. (author)
The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a highperformance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding...
conference paper 2013
document
Yuan, C. (author), Wei, J. (author), Ye, H. (author), Koh, S. (author), Harianto, S. (author), van den Nieuwenhof, M.A. (author), Zhang, G.Q. (author)
This paper demonstrates a heterogeneous integration of solid state lighting (SSL) module, including light source (LED) and driver/control components. Such integration has been realized by the polymer-based reconfigured wafer level package technologies and such structure has been prototyped and tested. The structure design, thermal design...
conference paper 2012
document
Saadaoui, M. (author), van Zeijl, H. (author), Wien, W.H.A. (author), Pham, H.T.M. (author), Kwakernaak, C. (author), Knoops, H.C.M. (author), Erwin Kessels, W.M.M. (author), van de Sanden, R.M.C.M. (author), Voogt, F.C. (author), Roozeboom, F. (author), Sarro, P.M. (author)
One of the critical steps toward producing void-free and uniform bottom-up copper electroplating in high aspect-ratio (AR) through-silicon vias (TSVs) is the ability of the copper electrolyte to spontaneously flow through the entire depth of the via. This can be accomplished by reducing the concentration gradient of cupric ions from the via...
article 2011
Searched for: subject%3A%22Wafer%255C%2Blevel%255C%2Bpackaging%22
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