Title
Schedule Synthesis for Halide Pipelines on GPUs
Author
Sioutas, S.
Stuijk, S.
Basten, T.
Corporaal, H.
Somers, L.
Publication year
2020
Abstract
The Halide DSL and compiler have enabled high-performance code generation for image processing pipelines targeting heterogeneous architectures through the separation of algorithmic description and optimization schedule. However, automatic schedule generation is currently only possible for multi-core CPU architectures. As a result, expert knowledge is still required when optimizing for platforms with GPU capabilities. In this work, we extend the current Halide Autoscheduler with novel optimization passes to efficiently generate schedules for CUDA-based GPU architectures. We evaluate our proposed method across a variety of applications and show that it can achieve performance competitive with that of manually tuned Halide schedules, or in many cases even better performance. Experimental results show that our schedules are on average 10% faster than manual schedules and over 2× faster than previous autoscheduling attempts.
Subject
Computer systems organization
Embedded systems
Software and its engineering
Compilers
Domain specific languages
Loop optimizations
Image processing
Halide
GPU
Scheduling
Industrial Innovation
To reference this document use:
http://resolver.tudelft.nl/uuid:fe1b61fe-e500-4a2d-b351-129fbf261231
DOI
https://doi.org/10.1145/3406117
TNO identifier
880334
Publisher
ACM
ISSN
1544-3566
Source
ACM Transactions on Architecture and Code Optimization, 17 (17)
Document type
conference paper